Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46556 )
Change subject: sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurable ......................................................................
Patch Set 23:
(5 comments)
https://review.coreboot.org/c/coreboot/+/46556/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46556/8//COMMIT_MSG@9 PS8, Line 9: Coperlake_SP
Co*o*perlake-SP
Done
https://review.coreboot.org/c/coreboot/+/46556/1/src/security/intel/txt/rams... File src/security/intel/txt/ramstage.c:
https://review.coreboot.org/c/coreboot/+/46556/1/src/security/intel/txt/rams... PS1, Line 318: sinit_size
on the deltalake board this needs an additional 64K. Not sure what is the case for other SoC's...
Done
https://review.coreboot.org/c/coreboot/+/46556/12/src/security/intel/txt/ram... File src/security/intel/txt/ramstage.c:
https://review.coreboot.org/c/coreboot/+/46556/12/src/security/intel/txt/ram... PS12, Line 307: /* Recent SINIT ACM (COOPERLAKE_SP) are 256KiB but also need 64KiB data size */
This comes from 572782.
Done
https://review.coreboot.org/c/coreboot/+/46556/12/src/security/intel/txt/ram... PS12, Line 306: define HEAP_SIZE (1 * MiB) : /* Recent SINIT ACM (COOPERLAKE_SP) are 256KiB but also need 64KiB data size */ : #define SINIT_SIZE ((256 + 64) * KiB)
Sounds good.
Done
https://review.coreboot.org/c/coreboot/+/46556/12/src/security/intel/txt/ram... PS12, Line 415: write64((void *)TXT_SINIT_SIZE, SINIT_SIZE);
This is not true anymore for Cooperlake_SP. […]
Done