Attention is currently required from: Julian Schroeder. Hello Julian Schroeder,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/58279
to review the following change.
Change subject: src/soc/amd/cezanne: enable clock gating ......................................................................
src/soc/amd/cezanne: enable clock gating
Enabling clock gating for CGPLL to lower power consumption in S3 and S0i3 states.
BUG=b:185273565 TEST=iotools mmio_read32 0xfed80e2c and 0e30 show clk gating enabled.
Change-Id: I33cbdeec62e49db90b680da37e5028df03a9c015 Signed-off-by: Julian Schroeder julianmarcusschroeder@gmail.com --- M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/include/soc/southbridge.h 2 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/58279/1
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index ac79cc9..bd08b66 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -169,6 +169,25 @@ misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); }
+ +static void cgpll_clock_gate_init(void) +{ + uint32_t t; + + t = misc_read32(MISC_CLKGATEDCNTL); + t |= ALINKCLK_GATEOFFEN; + t |= BLINKCLK_GATEOFFEN; + t |= XTAL_PAD_S3_TURNOFF_EN; + t |= XTAL_PAD_S5_TURNOFF_EN; + misc_write32(MISC_CLKGATEDCNTL, t); + + t = misc_read32(MISC_CGPLL_CONFIGURATION0); + t |= USB_PHY_CMCLK_S3_DIS; + t |= USB_PHY_CMCLK_S0I3_DIS; + t |= USB_PHY_CMCLK_S5_DIS; + misc_write32(MISC_CGPLL_CONFIGURATION0, t); +} + void fch_init(void *chip_info) { fch_init_resets(); @@ -181,6 +200,7 @@
gpp_clk_setup(); fch_clk_output_48Mhz(); + cgpll_clock_gate_init(); }
void fch_final(void *chip_info) diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 8a1150e..b031bdf 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -110,6 +110,15 @@ #define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) +#define MISC_CLKGATEDCNTL 0x2c +#define ALINKCLK_GATEOFFEN BIT(16) +#define BLINKCLK_GATEOFFEN BIT(17) +#define XTAL_PAD_S3_TURNOFF_EN BIT(20) +#define XTAL_PAD_S5_TURNOFF_EN BIT(21) +#define MISC_CGPLL_CONFIGURATION0 0x30 +#define USB_PHY_CMCLK_S3_DIS BIT(8) +#define USB_PHY_CMCLK_S0I3_DIS BIT(9) +#define USB_PHY_CMCLK_S5_DIS BIT(10)
void configure_port80_routing_early(void); void fch_pre_init(void);