[coreboot-gerrit] [S] Change in coreboot[main]: add CPU and PCIe definitions for SNR

[Jérémy Compostella (Code Review)]

Attention is currently required from: Shuo Liu, [e-mail].

Jérémy Compostella has posted comments on this change by [e-mail]. ( https://review.coreboot.org/c/coreboot/+/83314?usp=email )

Change subject: add CPU and PCIe definitions for SNR
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Patch Set 1:

(2 comments)

Patchset:

PS1: 
- Isn't it an EDS could you could reference in the commit message ?
- The list of files touched is short compared to https://review.coreboot.org/c/coreboot/+/62581 which was for Meteor Lake. Is this expected for SNR ?

File src/include/cpu/intel/cpu_ids.h:

https://review.coreboot.org/c/coreboot/+/83314/comment/e7a8663b_68e63d3d?usp... :
PS1, Line 86: #define CPUID_SNOWRIDGE_A0	0x80660
Isn't it missing an extra tab for indentation ?