Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56955 )
Change subject: mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cb ......................................................................
mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cb
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC.
BUG=None BRANCH=None TEST=Change has no functional impact on the brya board.
Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d Signed-off-by: MAULIK V VAGHELA maulik.v.vaghela@intel.com --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/chipset.cb 5 files changed, 2 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/56955/1
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 27f3211..2445987 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/tigerlake
- device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index abb8bdc..ae81518 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -79,8 +79,6 @@
chip soc/intel/tigerlake
- device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 66eb027..2b159d5 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/tigerlake
- device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c4bbdda..e55a73c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/tigerlake
- device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index e81f0524..4ebfcfd 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -1,4 +1,6 @@ chip soc/intel/tigerlake + + device cpu_cluster 0 on end device domain 0 on device gpio 0 alias pch_gpio on end device pci 00.0 alias system_agent on end