[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/fatcat: Remove redundant GPIOs for x1 slot

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85523?usp=email )

Change subject: mb/google/fatcat: Remove redundant GPIOs for x1 slot
......................................................................

mb/google/fatcat: Remove redundant GPIOs for x1 slot

The following GPIOs are already implemented in fw_config.c based on
CBI values:

- GPP_A08: X1_PCIE_SLOT_PWR_EN
- GPP_B25: X1_SLOT_WAKE_N
- GPP_D19: X1_DT_PCIE_RST_N

This change removes the redundant GPIO definitions from gpio.c.

BUG=b:376019977
TEST=Able to build and boot google/fatcat with functional x1 slot.

Change-Id: I56c6fd3ea8b9e58933548543d195621da94c882e
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/fatcat/variants/fatcat/gpio.c
1 file changed, 0 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/85523/1

diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 45cede6..5705179 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -28,8 +28,6 @@
    /* GPP_A06:     ESPI_RST_EC_R_N */
    /*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */

-	/* GPP_A08:     X1_PCIE_SLOT_PWR_EN */
-	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
    /* GPP_A09:     M.2_WWAN_FCP_OFF_N */
    PAD_CFG_GPO(GPP_A09, 1, PLTRST),
    /* GPP_A10:     M.2_WWAN_DISABLE_N */
@@ -101,8 +99,6 @@
    PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
    /* GPP_B24:     ESPI_ALERT0_EC_R_N */
    PAD_NC(GPP_B24, NONE),
-	/* GPP_B25:     X1_SLOT_WAKE_N */
-	PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),

/* GPP_C00:     GPP_C0_SMBCLK */
    PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
@@ -187,8 +183,6 @@
    PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
    /* GPP_D18:     CLKREQ6_X4_GEN4_M2_SSD_N */
    PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
-	/* GPP_D19:     X1_DT_PCIE_RST_N */
-	PAD_CFG_GPO(GPP_D19, 1, PLTRST),
    /* GPP_D20:     CSE_EARLY_SW */
    PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
    /* GPP_D21:     GPP_D21_UFS_REFCLK */