[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp/cpx: Fix register lock

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85439?usp=email )

Change subject: soc/intel/xeon_sp/cpx: Fix register lock
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soc/intel/xeon_sp/cpx: Fix register lock

Do not use a define for a PCI register to lock a MSR.

The defines will be moved in the following commit to it's own header,
preventing the use in CPX CPU init.

Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85439
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/xeon_sp/cpx/cpu.c
1 file changed, 1 insertion(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index d90b8b5..ae3f0fb 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -115,10 +115,8 @@
    set_vmx_and_lock();
    set_aesni_lock();

-	/* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions
-	   Lock Turbo. Did FSP-S set this up??? */
    msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO);
-	msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK);
+	msr.lo |= BIT31;	/* Lock it */
    wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr);
 }