[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/brox/jubilant: Update GPE0 routing

[Ren Kuo (Code Review)]

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84124?usp=email )

Change subject: mb/google/brox/jubilant: Update GPE0 routing
......................................................................

mb/google/brox/jubilant: Update GPE0 routing

Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1
---
M src/mainboard/google/brox/variants/jubilant/overridetree.cb
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/84124/1

diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb
index 0613ff9..f337334 100644
--- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb
+++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb
@@ -19,6 +19,12 @@
 end

chip soc/intel/alderlake
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_F"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
    register "platform_pmax" = "208"

register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # USB2_C0
@@ -448,7 +454,7 @@
    			register "uid" = "1"
    			register "compat_string" = ""google,cros-ec-spi""
    			register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
-				register "wake" = "GPE0_DW2_15"
+				register "wake" = "GPE0_DW1_15"
    			register "has_power_resource" = "1"
    			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"