[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: Preload uCode

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59506 )

Change subject: soc/amd/cezanne: Preload uCode
......................................................................

soc/amd/cezanne: Preload uCode

Reduces boot time by 1 ms.

BUG=b:179699789
TEST=Boot guybrush and verify 1ms reduction in boot time
| 112 - started reading uCode                         | 1.041     | 1.204     Δ(  0.16,    0.01%) |
| 113 - finished reading uCode                        | 1.365     | 0.011     Δ( -1.35,   -0.10%) |

Signed-off-by: Raul E Rangel 
Change-Id: I3bde5bd36489818b1a19b30490d7bb202c26ee34
---
M src/soc/amd/cezanne/fsp_s_params.c
M src/soc/amd/cezanne/preload.c
2 files changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/59506/1

diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index 93a5734..a015ef0 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -30,6 +30,5 @@
     * for the FSP-S preload has been freed, so we don't have to worry about exhausting the
     * cbfs_cache.
     */
-
    vga_oprom_preload();
 }
diff --git a/src/soc/amd/cezanne/preload.c b/src/soc/amd/cezanne/preload.c
index 43da4b6..6ad5c41 100644
--- a/src/soc/amd/cezanne/preload.c
+++ b/src/soc/amd/cezanne/preload.c
@@ -2,6 +2,7 @@

#include <acpi/acpi.h>
 #include <bootstate.h>
+#include <cpu/amd/microcode.h>
 #include <fsp/api.h>
 #include <program_loading.h>

@@ -18,6 +19,7 @@
  */
 static void start_post_elog_preloads(void *unused)
 {
+	preload_microcode();
    preload_acpi_dsdt();
    if (!acpi_is_wakeup_s3())
    	payload_preload();