[coreboot-gerrit] [M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...

[EricKY Cheng (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Tim Van Patten, Fred Reitberger, Felix Held.

EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 )

Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
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Patch Set 22:

(1 comment)

File src/soc/amd/mendocino/root_complex.c:

https://review.coreboot.org/c/coreboot/+/68649/comment/9303d429_cd0c4172 
PS16, Line 393: #else
> > I assume below behavior is your suggestion? […]

Update the code change after consulting AMD
1. Use #if (CONFIG(FEATURE_DYNAMIC_DPTC)) to include tables B through F.
2. Default Table A and no battery table use the Enhance DPTC_INPUT.
3. Support Enhance DPTC_INPUT structure directly, don't support old DPTC_INPUTS structure.
4. The update code change and design need to be verified by AMD and Google.

Hi AMD,

Since many default and low/now battery entries duplicated, do we need to expand the parameters for low/now battery in chip.h?