[coreboot-gerrit] Change in coreboot[master]: cpu/x86/mtrr: Correct displaying AMD fixed MTRRs

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60005 )

Change subject: cpu/x86/mtrr: Correct displaying AMD fixed MTRRs
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cpu/x86/mtrr: Correct displaying AMD fixed MTRRs

AMD Fixed MTRRs also contain DRAM read/write permissions which need to
be accounted for when determining the memory type. Apply the correct
mask on the MTRR type field when X86_AMD_FIXED_MTRRS are enabled.

Also expose the rwdram bits in the fixed MTRRs so that the printed MTRR
contents reflect the actual values stored in the registers. This allows
better validation of AMD fixed MTRRs.

TEST=Boot apu2 and display MTRRs. MTRR types reported are not reserved
and the output displays rwdram bits correctly. Example:

0x0000000000000508: IA32_MTRRCAP: WC, FIX, 8 variable MTRRs
0x0000000000000c06: IA32_MTRR_DEF_TYPE: E, FE, WB
0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX64K_00000
    0x00000000 - 0x0007ffff: WB
0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX16K_80000
    0x00080000 - 0x0009ffff: WB
0x0000000000000000: IA32_MTRR_FIX16K_A0000
    0x000a0000 - 0x000bffff: UC
0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_C0000
    0x000c0000 - 0x000c7fff: WB
0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_C8000
    0x000c8000 - 0x000cffff: WB
0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_D0000
    0x000d0000 - 0x000d7fff: WB
0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_D8000
    0x000d8000 - 0x000dffff: WB
0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_E0000
    0x000e0000 - 0x000e7fff: WB
0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_E8000
    0x000e8000 - 0x000effff: WB
0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_F0000
    0x000f0000 - 0x000f7fff: WB
0x1e1e1e1e1e1e1e1e: IA32_MTRR_FIX4K_F8000
    0x000f8000 - 0x000fffff: WB

Signed-off-by: Michał Żygowski 
Change-Id: Id9951f5e3702c04a4b06f6bf0de2f264d13292af
---
M src/cpu/x86/mtrr/Makefile.inc
M src/cpu/x86/mtrr/debug.c
M src/cpu/x86/mtrr/earlymtrr.c
3 files changed, 34 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60005/1

diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc
index 3f33e31..a78517a 100644
--- a/src/cpu/x86/mtrr/Makefile.inc
+++ b/src/cpu/x86/mtrr/Makefile.inc
@@ -3,6 +3,7 @@
 romstage-y	+= earlymtrr.c
 bootblock-y	+= earlymtrr.c
 verstage_x86-y	+= earlymtrr.c
+postcar-y	+= earlymtrr.c

bootblock-y	+= debug.c
 romstage-y	+= debug.c
diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c
index 4ecae06..f8ae14c 100644
--- a/src/cpu/x86/mtrr/debug.c
+++ b/src/cpu/x86/mtrr/debug.c
@@ -28,12 +28,16 @@
    uint32_t type;

type = msr & MTRR_DEF_TYPE_MASK;
+	if (CONFIG(X86_AMD_FIXED_MTRRS))
+		type &= 0x07;
    base_address = starting_address;
    next_address = base_address;
    for (index = 0; index < 64; index += 8) {
    	next_address = starting_address + (memory_size *
    		((index >> 3) + 1));
    	next_type = (msr >> index) & MTRR_DEF_TYPE_MASK;
+		if (CONFIG(X86_AMD_FIXED_MTRRS))
+			next_type &= 0x07;
    	if (next_type != type) {
    		printk(BIOS_DEBUG, "    0x%08x - 0x%08x: %s\n",
    			base_address, next_address - 1,
@@ -160,6 +164,8 @@
    int i;
    int variable_mtrrs;

+	fixed_mtrrs_expose_amd_rwdram();
+
    /* Display the fixed MTRRs */
    display_mtrrcap();
    display_mtrr_def_type();
@@ -177,6 +183,8 @@
    address_bits = cpu_phys_address_size();
    address_mask = (1ULL << address_bits) - 1;

+	fixed_mtrrs_hide_amd_rwdram();
+
    /* Display the variable MTRRs */
    variable_mtrrs = get_var_mtrr_count();
    for (i = 0; i < variable_mtrrs; i++)
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index aa301d0..b003291 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -1,11 +1,36 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <cpu/cpu.h>
+#include <cpu/amd/mtrr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <console/console.h>
 #include <commonlib/bsd/helpers.h>

+void fixed_mtrrs_expose_amd_rwdram(void)
+{
+	msr_t syscfg;
+
+	if (!CONFIG(X86_AMD_FIXED_MTRRS))
+		return;
+
+	syscfg = rdmsr(SYSCFG_MSR);
+	syscfg.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, syscfg);
+}
+
+void fixed_mtrrs_hide_amd_rwdram(void)
+{
+	msr_t syscfg;
+
+	if (!CONFIG(X86_AMD_FIXED_MTRRS))
+		return;
+
+	syscfg = rdmsr(SYSCFG_MSR);
+	syscfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, syscfg);
+}
+
 /* Get first available variable MTRR.
  * Returns var# if available, else returns -1.
  */