[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/block/lpc: Add config options for eSPI

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41069 )

Change subject: soc/amd/common/block/lpc: Add config options for eSPI
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41069/1/src/soc/amd/common/block/lp... 
File src/soc/amd/common/block/lpc/Kconfig:

https://review.coreboot.org/c/coreboot/+/41069/1/src/soc/amd/common/block/lp... 
PS1, Line 19: 	  Select this option if mainboard uses eSPI instead of LPC (if supported
> Please see my comment5 on b/154445472. […]

I agree with Felix, we should cleanly support both espi and lpc. I also believe it will help with clarity when looking at the device tree. I like your idea about adding a new bus. I threw up a WIP CL that adds espi and lpc buses: https://review.coreboot.org/c/coreboot/+/41099 I can finish it up if you want.

Not sure what you are thinking about eSPI config, but having the bus, we could also have a chip specific config:

device pci 14.3 on  # - D14F3 bridge
    chip soc/amd/common/espi
    	register "bus_width" = "ESPI_IO_MODE_QUAD"
    	register "espi_freq_mhz" = "ESPI_OP_FREQ_33_MHZ"
    	device espi 0 on
    		chip ec/google/chromeec
    			device pnp 0c09.0 on end
    		end
    	end
    end
end

Thoughts?