[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/volteer/var/drobit: Set UART GPIOs in bootblock

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83995?usp=email )

Change subject: mb/google/volteer/var/drobit: Set UART GPIOs in bootblock
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mb/google/volteer/var/drobit: Set UART GPIOs in bootblock

Enables early serial console for debugging.

TEST=build/boot drobit, verify console output available starting in
bootblock on CPU UART (/dev/ttyUSB1) vs ramstage.

Change-Id: If94eb8caca3469143433fef06b972050f886be6a
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83995
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Singer 
---
M src/mainboard/google/volteer/variants/drobit/gpio.c
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  Felix Singer: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/volteer/variants/drobit/gpio.c b/src/mainboard/google/volteer/variants/drobit/gpio.c
index f7ee4eef..f36b89c 100644
--- a/src/mainboard/google/volteer/variants/drobit/gpio.c
+++ b/src/mainboard/google/volteer/variants/drobit/gpio.c
@@ -135,6 +135,11 @@

/* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
+	/* C8 : UART0 RX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9 : UART0 TX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+
    /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
    PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
    /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */