[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable CPU PCIE in FSP

[Shaunak Saha (Code Review)]

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )

Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP
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Patch Set 3:

(8 comments)

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@7 
PS3, Line 7: PCIE
> PCIe

Will fix

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 
PS3, Line 9: iIn
> In?

Will fix

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 
PS3, Line 9: Pcie
> PCIe

Will fix

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 
PS3, Line 9: soc
> SoC

Will fix

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@10 
PS3, Line 10: Pcie
> PCIe

Will fix

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@11 
PS3, Line 11: Pcie
> PCIe

Will fix

https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@18 
PS3, Line 18: this patch.
> Tiiight, but it does if split up like this: […]

Will fix

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... 
PS3, Line 208: 0
> Right, so it would be good to add that 0:6.0 device in `soc/pci_devs.h` and then do: […]

Thanks for the review.
I will add 0:6.0 device in pci_devs.h and change this code to:
dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
 m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;