[coreboot-gerrit] Change in coreboot[master]: mb/google/brya/var/agah: Add TcssAuxOri settings for Port 0

[Tony Huang (Code Review)]

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61795 )

Change subject: mb/google/brya/var/agah: Add TcssAuxOri settings for Port 0
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mb/google/brya/var/agah: Add TcssAuxOri settings for Port 0

Agah port 0 does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.

Set the TcssAuxOri and add "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages.

BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
when the cable is flipped

Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa
Signed-off-by: Tony Huang 
---
M src/mainboard/google/brya/variants/agah/overridetree.cb
1 file changed, 4 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/61795/1

diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb
index 3856df2..f890582 100644
--- a/src/mainboard/google/brya/variants/agah/overridetree.cb
+++ b/src/mainboard/google/brya/variants/agah/overridetree.cb
@@ -1,5 +1,4 @@
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |
@@ -31,6 +30,10 @@
    	},
    }"

+	register "SaGv" = "SaGv_Enabled"
+	register "TcssAuxOri" = "1"
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+
    register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Disable USB2_C1
    register "usb2_ports[3]" = "USB2_PORT_EMPTY"		# Disable M.2 WWAN
    register "usb2_ports[4]" = "USB2_PORT_EMPTY"		#