[coreboot-gerrit] [S] Change in coreboot[master]: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes

[Mario Scheithauer (Code Review)]

Attention is currently required from: Werner Zeh.

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74650 )

Change subject: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes
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mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes

On this mainboard NC FPGA is connected to PCIe root port #1 (00:1c.0).
To get the POST codes in coreboot, correct the Kconfig switch
EARLY_PCI_BRIDGE_FUNCTION to '0'.

Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
1 file changed, 15 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/74650/1

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
index ee725cc..21789d7 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
@@ -22,7 +22,7 @@
 config EARLY_PCI_BRIDGE_FUNCTION
    hex
    depends on NC_FPGA_POST_CODE
-	default 0x2
+	default 0x0

config EARLY_PCI_MMIO_BASE
    hex