Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42062 )
Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ......................................................................
src/*: Update makefiles to exclude x86 code from non-x86 verstage
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP.
BUG=b:158124527 TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I797b67394825172bd44ad1ee693a0c509289486b --- M src/arch/x86/Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc 9 files changed, 58 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42062/1
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0dd8d2b..6446043 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -83,32 +83,24 @@ endef
############################################################################### -# all (bootblock,verstage,romstage,postcar,ramstage) -############################################################################### - -ifeq ($(CONFIG_ARCH_X86),y) - -all-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c -all-y += boot.c -all-y += memcpy.c -all-y += memset.c -all-y += cpu_common.c -all-y += post.c - -endif - -############################################################################### # bootblock ###############################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
+bootblock-y += boot.c +bootblock-y += post.c +bootblock-y += cpu_common.c bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S +bootblock-y += memcpy.c +bootblock-y += memset.c bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c bootblock-y += id.S +bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c + $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
bootblock-y += bootblock_crt0.S @@ -129,10 +121,16 @@
ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
+verstage-y += boot.c +verstage-y += post.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S +verstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
+verstage-y += cpu_common.c +verstage-y += memset.c +verstage-y += memcpy.c verstage-y += memmove.c verstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c # If verstage is a separate stage it means there's no need @@ -161,16 +159,22 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +romstage-y += boot.c +romstage-y += post.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. romstage-y += gdt_init.S romstage-y += cbmem.c +romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S +romstage-y += memcpy.c romstage-y += memmove.c +romstage-y += memset.c romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c romstage-y += postcar_loader.c romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c) romstage-libs ?= @@ -196,15 +200,21 @@ postcar-generic-ccopts += -D__POSTCAR__
postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +postcar-y += boot.c +postcar-y += post.c postcar-y += gdt_init.S +postcar-y += cpu_common.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S +postcar-y += memcpy.c postcar-y += memmove.c +postcar-y += memset.c postcar-y += memlayout.ld postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +postcar-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
LDFLAGS_postcar += -Map $(objcbfs)/postcar.map
@@ -229,15 +239,20 @@
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c +ramstage-y += boot.c +ramstage-y += post.c ramstage-y += c_start.S ramstage-y += cpu.c +ramstage-y += cpu_common.c ramstage-y += ebda.c ramstage-y += exception.c ramstage-y += idt.S ramstage-y += gdt.c ramstage-$(CONFIG_IOAPIC) += ioapic.c +ramstage-y += memcpy.c ramstage-y += memlayout.ld ramstage-y += memmove.c +ramstage-y += memset.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c @@ -248,6 +263,7 @@ ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S +ramstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) rmodules_x86_32-y += memcpy.c diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 0d11478..a35433e 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -6,7 +6,9 @@ ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += boot_cpu.c +endif romstage-y += boot_cpu.c ramstage-y += boot_cpu.c postcar-y += boot_cpu.c diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 129d05d..3a5ba88 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -2,7 +2,10 @@
romstage-y += earlymtrr.c bootblock-y += earlymtrr.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += earlymtrr.c +verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c +endif
bootblock-y += debug.c romstage-y += debug.c @@ -10,4 +13,3 @@ ramstage-y += debug.c
bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c -verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc index 62176d2..7825db8 100644 --- a/src/cpu/x86/pae/Makefile.inc +++ b/src/cpu/x86/pae/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += pgtbl.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += pgtbl.c +endif romstage-y += pgtbl.c postcar-y += pgtbl.c ramstage-y += pgtbl.c diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index b3925b5..d8f44d9 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,8 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +endif postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 67c40a1..e591dd1 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -7,7 +7,9 @@ romstage-$(CONFIG_SPKMODEM) += spkmodem.c
bootblock-y += i8254.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += i8254.c +endif romstage-y += i8254.c ramstage-y += i8254.c postcar-y += i8254.c diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index 708631a..27876aa 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -1,5 +1,7 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +endif romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c diff --git a/src/soc/amd/common/block/alink/Makefile.inc b/src/soc/amd/common/block/alink/Makefile.inc index 720a7cb..e9d8612 100644 --- a/src/soc/amd/common/block/alink/Makefile.inc +++ b/src/soc/amd/common/block/alink/Makefile.inc @@ -1,5 +1,7 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +endif romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 558a7ac..c5568d4 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,4 +1,14 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y)
-ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c +ramstage-y += amd_pci_util.c
-all-y += amd_pci_mmconf.c +bootblock-y += amd_pci_mmconf.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) +verstage-y += amd_pci_mmconf.c +endif +romstage-y += amd_pci_mmconf.c +postcar-y += amd_pci_mmconf.c +ramstage-y += amd_pci_mmconf.c +smm-y += amd_pci_mmconf.c + +endif