Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43906 )
Change subject: mb/intel/kunimitsu: Relocate devicetree FSP settings ......................................................................
mb/intel/kunimitsu: Relocate devicetree FSP settings
Also, explicitly set some settings to zero. These will be cleaned up in follow-ups, which will be easier to review if the current value for this option gets removed in those follow-ups.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I1d821671b3078f83ec988c9930730eaa75599290 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/kunimitsu/devicetree.cb 1 file changed, 41 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/43906/1
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 51ff562..9399e26 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -24,16 +24,9 @@ register "dptf_enable" = "1"
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "1"
@@ -117,16 +110,6 @@ .voltage_limit = 1520, }"
- # Enable Root port 1 and 5. - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkReqNumber[4]" = "2" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth @@ -139,8 +122,6 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
- register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \ @@ -164,9 +145,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" - # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -178,6 +156,10 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + + # FIXME: corresponding device entry is missing + register "Device4Enable" = "1" + device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem @@ -200,7 +182,11 @@ end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -208,7 +194,8 @@ device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 - device pci 19.2 on + device pci 19.2 on # I2C #4 + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V chip drivers/i2c/nau8825 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" register "jkdet_enable" = "1" @@ -245,17 +232,24 @@ register "device_present_gpio" = "GPP_E3" device i2c 35 on end end - end # I2C #4 - device pci 1c.0 on + end + device pci 1c.0 on # PCI Express Port 1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" device pci 00.0 on end end - end # PCI Express Port 1 + end device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 @@ -267,9 +261,17 @@ device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC + device pci 1e.4 on # eMMC + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + end device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard + device pci 1e.6 on # SDCard + register "ScsSdCardEnabled" = "2" + + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_A7" + end device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end @@ -281,6 +283,7 @@ device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on + register "EnableAzalia" = "1" chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" @@ -289,8 +292,14 @@ device generic 0 on end end end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end end