[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/common/block/fast_spi: probe for 2nd flash component

[Maciej Pijanowski (Code Review)]

Hello Michał Żygowski,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/80608?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/common/block/fast_spi: probe for 2nd flash component
......................................................................

soc/intel/common/block/fast_spi: probe for 2nd flash component

Fast SPI code assumes only one SPI flash is present. The SPI flash
driver for older southbridges used to be able to detect multichip.

Some boards still come with two chips populated instead of one.
With this change, both chips are probed, and the correct total
size is calculated. Otherwise, only the first one was probed,
which resulted in an error such as:

SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x1800000!!

Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c
Signed-off-by: Michał Żygowski 
Signed-off-by: Maciej Pijanowski 
---
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
2 files changed, 30 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/80608/2