Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43915 )
Change subject: mb/intel/kblrvp/var/rvp11: Relocate devicetree FSP settings ......................................................................
mb/intel/kblrvp/var/rvp11: Relocate devicetree FSP settings
Almost all PCIe root ports enabled in FSP are not declared in neither the devicetree nor the overridetree. Put FIXMEs on these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I19050629fdb0f024ecb342830a05d021ee416a4c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb 1 file changed, 75 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/43915/1
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 98ab6df..ed1a7e0 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -1,56 +1,11 @@ chip soc/intel/skylake
# FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "0" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "Device4Enable" = "0" - register "Heci3Enabled" = "0" register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"
- # Enable PCIE slot - register "PcieRpEnable[5]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 - # RP6, uses uses CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - register "PcieRpEnable[6]" = "1" - register "PcieRpClkReqSupport[6]" = "1" - register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 - # RP7, uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[6]" = "2" - - register "PcieRpEnable[7]" = "1" - register "PcieRpClkReqSupport[7]" = "1" - register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - # RP8, uses uses CLK SRC 3 - register "PcieRpClkSrcNumber[7]" = "3" - - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - # RP9, uses uses CLK SRC 4 - register "PcieRpClkSrcNumber[8]" = "4" - - register "PcieRpEnable[13]" = "1" - register "PcieRpClkReqSupport[13]" = "1" - register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 - # RP14, uses uses CLK SRC 5 - register "PcieRpClkSrcNumber[13]" = "5" - - register "PcieRpEnable[16]" = "1" - register "PcieRpClkReqSupport[16]" = "1" - register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 - # RP17, uses uses CLK SRC 7 - register "PcieRpClkSrcNumber[16]" = "7" - - register EnableLan = "1" - # USB related register "SsicPortEnable" = "1"
@@ -80,21 +35,6 @@ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
- - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ - }" register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \ [PchSerialIoIndexI2C1] = PchSerialIoPci, \ @@ -119,17 +59,87 @@
# Lock Down register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }"
device domain 0 on - device pci 17.0 on end # SATA + + # Disable SA thermal device + register "Device4Enable" = "0" + + # Disable HECI 3 + register "Heci3Enabled" = "0" + + device pci 17.0 on # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + end device pci 19.1 on end # I2C #5 + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # FIXME: Corresponding device entry missing + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "1" + + # FIXME: Corresponding device entry missing + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "2" + register "PcieRpClkSrcNumber[6]" = "2" + + # FIXME: Corresponding device entry missing + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" + register "PcieRpClkSrcNumber[7]" = "3" + + # The device entry for this is in the devicetree + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + register "PcieRpClkSrcNumber[8]" = "4" + + # FIXME: Corresponding device entry missing + register "PcieRpEnable[13]" = "1" + register "PcieRpClkReqSupport[13]" = "1" + register "PcieRpClkReqNumber[13]" = "5" + register "PcieRpClkSrcNumber[13]" = "5" + + # FIXME: Corresponding device entry missing + register "PcieRpEnable[16]" = "1" + register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqNumber[16]" = "7" + register "PcieRpClkSrcNumber[16]" = "7" + device pci 1e.1 on end # UART #1 device pci 1e.2 on end # GSPI #0 device pci 1e.3 on end # GSPI #1 - device pci 1e.4 off end # eMMC - device pci 1e.6 off end # SDCard - device pci 1f.6 on end # GbE + device pci 1e.4 off # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + end + device pci 1e.6 off # SDCard + register "ScsSdCardEnabled" = "0" + end + + # Enable Intel HD + register "EnableAzalia" = "1" + + device pci 1f.6 on # GbE + register EnableLan = "1" + end end end