King Sumo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56975 )
Change subject: soc/intel/denverton_ns: Add GPIO controller ASL ......................................................................
soc/intel/denverton_ns: Add GPIO controller ASL
Add support for the pinctrl denverton Linux driver which provides an interface that allows configuring of Intel Denverton SoC pins and using them as GPIOs.
Test using the sysfs interface: - Load the pinctrl-denverton module, sysfs interface available in the /sys/kernel/debug/pinctrl/INTC3000:00 folder. - Export the GPIO (here we are using GPIO_10): ~> cd /sys/kernel/debug/pinctrl/INTC3000:00/ ~> grep GPIO_10 pinconf-pins pin 139 (GPIO_10): input bias disabled ~> cat gpio-ranges GPIO ranges handled: 0: INTC3000:00 GPIOS [358 - 511] PINS [0 - 153] ~> echo $((358+139)) > /sys/class/gpio/export - Above GPIO's are starting at 358 with GPIO_10 at 139 offset, the sysfs folder for controlling the pin will be /sys/class/gpio/gpio497 (358+139). - Input mode: ~> cd /sys/class/gpio/gpio497 ~> echo in > direction ~> cat value 0 ~> cat value 1 - Output mode: ~> cd /sys/class/gpio/gpio497 ~> echo out > direction ~> echo 1 > value ~> echo 0 > value
Signed-off-by: King Sumo kingsumos@gmail.com Change-Id: I9ca5df7b2e9b525424fc6c7260794f1d500a3c78 --- A src/soc/intel/denverton_ns/acpi/gpio.asl M src/soc/intel/denverton_ns/acpi/southcluster.asl 2 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/56975/1
diff --git a/src/soc/intel/denverton_ns/acpi/gpio.asl b/src/soc/intel/denverton_ns/acpi/gpio.asl new file mode 100644 index 0000000..dd8532f --- /dev/null +++ b/src/soc/intel/denverton_ns/acpi/gpio.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (GPIO) +{ + Name (_HID, "INTC3000") // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_DDN, "GPIO Controller") // _DDN: DOS Device Name + Name (_CRS, ResourceTemplate() // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xFDC20000, // Address Base + 0x00001000, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xFDC50000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) + { 14, } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0xF) + } +} diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index 72e12bd..e2169d7 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -104,6 +104,9 @@ Name (_ADR, 0x001C0000) }
+// GPIO controller +#include "gpio.asl" + // LPC Bridge 0:1f.0 #include "lpc.asl"