Hello Shelley Chen, build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Patrick Georgi, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, Sowmya V, Aamir Bohra, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42440
to look at the new patch set (#10).
Change subject: soc/intel/cannonlake: Add PchPmPwrCycDur to chip options ......................................................................
soc/intel/cannonlake: Add PchPmPwrCycDur to chip options
Add PchPmPwrCycDur to chip options to control the UPD FSPS PchPmPwrCycDur from devicetree. The UPD determines the minimum time a platform will stay in reset during host partition reset with power cycle or global reset. This patch also ensures configured PchPmPwrCycDur value doesn't violate the PCH EDS specification.
TEST=Verified on Hatch and Puff boards
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I55e836c78fab34e34d57b04428a1498b7dc7174b --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 148 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42440/10