Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40756 )
Change subject: soc/intel/cannonlake: Add DisableHeciRetry to config ......................................................................
soc/intel/cannonlake: Add DisableHeciRetry to config
Add DisableHeciRetry to the chip config and parse it in romstage.
Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf Signed-off-by: Christian Walter christian.walter@9elements.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/40756/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 578473b..981c381 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -195,6 +195,7 @@
/* Heci related */ uint8_t Heci3Enabled; + uint8_t DisableHeciRetry;
/* Gfx related */ uint8_t IgdDvmt50PreAlloc; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 010d152c..c99f5a5 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -128,6 +128,8 @@ config->sata_port[i].TxGen3DeEmph; } } + if (config->DisableHeciRetry) + tconfig->DisableHeciRetry = config->DisableHeciRetry; }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)