Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Christian Walter, Jes Klinke, Julius Werner, Patrick Rudolph, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43741
to look at the new patch set (#26).
Change subject: drivers/spi/tpm: Enable long cr50 ready pulses for Tiger Lake systems ......................................................................
drivers/spi/tpm: Enable long cr50 ready pulses for Tiger Lake systems
For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4 only if we know that the Cr50 is generating 100us interrupt pulses. We have to do so, because the SoC is not guaranteed to detect pulses shorter than 100us in S0i3.4 substate.
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, provided that Cr50 firmware is new enough to support the register.
BUG=b:154333137 TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
Signed-off-by: Jes Bodi Klinke jbk@chromium.org Change-Id: If83188fd09fe69c2cda4ce1a8bf5b2efe1ca86da --- M src/drivers/spi/tpm/tpm.c M src/drivers/spi/tpm/tpm.h M src/security/tpm/tss/vendor/cr50/Kconfig 3 files changed, 144 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/43741/26