Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51235 )
Change subject: soc/intel/broadwell/pch: Use Lynx Point smbus.c ......................................................................
soc/intel/broadwell/pch: Use Lynx Point smbus.c
Continue unifying Lynx Point and Wildcat Point (PCH for Broadwell) code. Define the WPT-LP SMBus PCI device ID, add it to smbus.c of Lynx Point, and drop all now-unnecessary SMBus code from Broadwell.
Change-Id: I864d7c2dd47895a3c559e2f1219425cda9fd0c17 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/51235 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/include/device/pci_ids.h D src/soc/intel/broadwell/include/soc/smbus.h M src/soc/intel/broadwell/pch/Makefile.inc M src/soc/intel/broadwell/pch/early_pch.c D src/soc/intel/broadwell/pch/smbus.c M src/southbridge/intel/lynxpoint/smbus.c 6 files changed, 3 insertions(+), 79 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d99f307..b54de0b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3911,6 +3911,7 @@ /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 #define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22 +#define PCI_DEVICE_ID_INTEL_WPT_LP_SMBUS 0x9ca2 #define PCI_DEVICE_ID_INTEL_APL_SMBUS 0x5ad4 #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123 diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/soc/intel/broadwell/include/soc/smbus.h deleted file mode 100644 index 80d92ac..0000000 --- a/src/soc/intel/broadwell/include/soc/smbus.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_SMBUS_H_ -#define _BROADWELL_SMBUS_H_ - -/* PCI Configuration Space (D31:F3): SMBus */ -#define SMB_BASE 0x20 -#define HOSTC 0x40 -#define HST_EN (1 << 0) - -/* SMBus I/O bits. */ -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define SMBUS_TIMEOUT (10 * 1000 * 100) -#define SMBUS_SLAVE_ADDR 0x24 - -#endif diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 740c7111..42d8df1 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -26,7 +26,7 @@ ramstage-y += ramstage.c ramstage-y += sata.c ramstage-y += serialio.c -ramstage-y += smbus.c +ramstage-y += ../../../../southbridge/intel/lynxpoint/smbus.c ramstage-y += smi.c smm-y += smihandler.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c diff --git a/src/soc/intel/broadwell/pch/early_pch.c b/src/soc/intel/broadwell/pch/early_pch.c index 5e7ce2a..cb45971 100644 --- a/src/soc/intel/broadwell/pch/early_pch.c +++ b/src/soc/intel/broadwell/pch/early_pch.c @@ -11,7 +11,6 @@ #include <soc/pm.h> #include <soc/rcba.h> #include <soc/romstage.h> -#include <soc/smbus.h> #include <soc/intel/broadwell/pch/chip.h>
static void pch_route_interrupts(void) diff --git a/src/soc/intel/broadwell/pch/smbus.c b/src/soc/intel/broadwell/pch/smbus.c deleted file mode 100644 index bd57b0a..0000000 --- a/src/soc/intel/broadwell/pch/smbus.c +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/path.h> -#include <device/smbus.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/smbus_host.h> -#include <southbridge/intel/common/smbus_ops.h> -#include <soc/smbus.h> - -static void pch_smbus_init(struct device *dev) -{ - struct resource *res; - u16 reg16; - - /* Enable clock gating */ - /* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */ - reg16 = pci_read_config32(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); - pci_write_config32(dev, 0x80, reg16); - - /* Set Receive Slave Address */ - res = find_resource(dev, PCI_BASE_ADDRESS_4); - if (res) - smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); -} - -static struct device_operations smbus_ops = { - .read_resources = smbus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_smbus, - .init = pch_smbus_init, - .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &pci_dev_ops_pci, -}; - -static const unsigned short pci_device_ids[] = { - 0x9c22, /* LynxPoint */ - 0x9ca2, /* WildcatPoint */ - 0 -}; - -static const struct pci_driver pch_smbus __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index e2d42ac..32c9c14 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -40,6 +40,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_LPT_H_SMBUS, PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS, + PCI_DEVICE_ID_INTEL_WPT_LP_SMBUS, 0 };