[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add and enable BROKEN_FSP_NEEDS_STACK_ABOVE_BSS

[Johnny Lin (Code Review)]

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74297 )

Change subject: soc/intel/xeon_sp/spr: Add and enable BROKEN_FSP_NEEDS_STACK_ABOVE_BSS
......................................................................

soc/intel/xeon_sp/spr: Add and enable BROKEN_FSP_NEEDS_STACK_ABOVE_BSS

Change-Id: I4a593252bb7f68494f4ccce215ac9cf1eb19b190
Signed-off-by: Johnny Lin 
---
M src/soc/intel/xeon_sp/spr/Kconfig
1 file changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/74297/1

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 832aab5..455d7fc 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -103,6 +103,17 @@
      documentation says this needs to be at least 128KiB, but practice
      show this needs to be 256KiB or more.

+config BROKEN_FSP_NEEDS_STACK_ABOVE_BSS
+	bool
+	default y
+	depends on FSP_USES_CB_STACK
+	help
+	 Starting with Intel CPX there is a bug in there reference code during
+	 the Pipe init. This code synchronises the CAR between sockets in FSP-M.
+	 The code implicitly assumes that the stack in use is above the FSP heap,
+	 which is confusingly configured with FspStackBase. This issue is only
+	 present on multi socket systems. This is a FSP spec violation.
+
 config IED_REGION_SIZE
    hex
    default 0x400000