[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/common/cnvi: Fix GBTE path in comment

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84991?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/common/cnvi: Fix GBTE path in comment
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soc/intel/common/cnvi: Fix GBTE path in comment

Change-Id: If1e5d70a23c2a139ef3ee4970db2e5d528c2661e
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84991
Reviewed-by: Nicholas Sudsgaard 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/cnvi/cnvi.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Nicholas Sudsgaard: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index b995ef3..d50913f 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -129,7 +129,7 @@
  *					If (((PCRR (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR) & CNVI_ABORT_REQUEST) == Zero))
  *					{
  *						Local2 = Zero
- *						If ((GBTE() == One))
+ *						If ((_SB.PCI0.GBTE() == One))
  *						{
  *							_SB.PCI0.BTRK (Zero)
  *							Sleep (105)