Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4864
-gerrit
commit 3fa81d22bb85d1e20b20df5d0ba8973fd2f8140c Author: Aaron Durbin adurbin@chromium.org Date: Fri Oct 4 11:17:45 2013 -0500
baytrail: initialize punit
The punit is responsible for a number of things. Without performing the sequence included it won't change processor frequency when requested and apparently there are some bizarre hangs introduced if this sequence isn't included either. Lastly, this needs to come after microcode has been loaded. As that is done in bootblock the ordering is correct.
One other side effect is that this fixes the graphics devices' device id. Before it was showing up as the same device id of the SoC transaction router.
BUG=chrome-os-partner:22880 BUG=chrome-os-partner:23085 BUG=chrome-os-partner:22876 BRANCH=None TEST=Built and booted.
Change-Id: Ib7be1d4b365e9a45647c778ee5f91de497c55bf1 Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: https://chromium-review.googlesource.com/171862 Reviewed-by: Shawn Nematbakhsh shawnn@chromium.org --- src/soc/intel/baytrail/baytrail/romstage.h | 1 + src/soc/intel/baytrail/romstage/pmc.c | 20 ++++++++++++++++++++ src/soc/intel/baytrail/romstage/romstage.c | 2 ++ 3 files changed, 23 insertions(+)
diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/baytrail/romstage.h index 760905c..4918a02 100644 --- a/src/soc/intel/baytrail/baytrail/romstage.h +++ b/src/soc/intel/baytrail/baytrail/romstage.h @@ -48,6 +48,7 @@ void asmlinkage romstage_after_car(void); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); +void punit_init(void);
#if CONFIG_ENABLE_BUILTIN_COM1 void byt_config_com1_and_enable(void); diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 414a6bb..6bd7805 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -34,3 +34,23 @@ void tco_disable(void) outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); }
+/* This sequence signals the PUNIT to start running. */ +void punit_init(void) +{ + uint32_t reg; + + /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ + reg = SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; + pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); + reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | + IOSF_REG(SB_BIOS_CONFIG) | IOSF_BYTE_EN_2; + pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); + + /* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ + reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE; + pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); + reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | + IOSF_REG(BIOS_RESET_CPL) | IOSF_BYTE_EN_0; + pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); +} + diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 3704069..6e965bc 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -126,6 +126,8 @@ void romstage_common(struct romstage_params *params)
console_init();
+ punit_init(); + gfx_init();
mark_ts(params, timestamp_get());