Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11006
-gerrit
commit d08ca115a0c20f1be8a832fdaeaff012533819f2 Author: Aaron Durbin adurbin@chromium.org Date: Thu Jul 16 17:49:33 2015 -0500
skylake: read out and report full width of gen_pmcon registers
GEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and save the full 32 bits for completeness.
BUG=chrome-os-partner:42847 BRANCH=None TEST=Built and booted. Noted output on terminal.
Change-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0 Original-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb Original-Signed-off-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/286270 Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org --- src/soc/intel/skylake/include/soc/pm.h | 4 ++-- src/soc/intel/skylake/romstage/power_state.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 3be83f4..4d9abcb 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -124,8 +124,8 @@ struct chipset_power_state { uint16_t tco2_sts; uint32_t gpe0_sts[4]; uint32_t gpe0_en[4]; - uint16_t gen_pmcon_a; - uint16_t gen_pmcon_b; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; int prev_sleep_state; uint16_t hsio_version; uint16_t hsio_checksum; diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index 7a6c8b3..4ffa381 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -95,7 +95,7 @@ static void dump_power_state(struct chipset_power_state *ps) ps->gpe0_en[0], ps->gpe0_en[1], ps->gpe0_en[2], ps->gpe0_en[3]);
- printk(BIOS_DEBUG, "GEN_PMCON: %04x %04x\n", + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b);
printk(BIOS_DEBUG, "Previous Sleep State: S%d\n", @@ -124,8 +124,8 @@ struct chipset_power_state *fill_power_state(void) ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2)); ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
- ps->gen_pmcon_a = pci_read_config16(PCH_DEV_PMC, GEN_PMCON_A); - ps->gen_pmcon_b = pci_read_config16(PCH_DEV_PMC, GEN_PMCON_B); + ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); + ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
ps->prev_sleep_state = prev_sleep_state(ps);