Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38461 )
Change subject: soc/intel/tigerlake: Update fsp params for Jasper Lake ......................................................................
Patch Set 18:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38461/16/src/soc/intel/tigerlake/ch... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38461/16/src/soc/intel/tigerlake/ch... PS16, Line 208: enum { : DEBUG_INTERFACE_RAM = 0x1, : DEBUG_INTERFACE_UART = 0x2, : DEBUG_INTERFACE_USB3 = 0x4, : DEBUG_INTERFACE_SERIAL_IO = 0x8, : DEBUG_INTERFACE_TRACEHUB = 0x10 : } debug_interface_flag;
the description seems to be incorrect, I see, it is getting used for IO UART read/write in the fsp.
The description does not say about UART. It is saying about the bits for USB3, SERIAL_IO & TRACEHUB i.e DEBUG_INTERFACE_USB3 should be 0x8 and not 0x4, DEBUG_INTERFACE_SERIAL_IO should be 0x10 and DEBUG_INTERFACE_TRACEHUB should be 0x20.
https://review.coreboot.org/c/coreboot/+/38461/16/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/38461/16/src/soc/intel/tigerlake/ro... PS16, Line 67: config->PcieClkSrcUsage[i] == 0
if config does not get set explicity through the devicetree(remains 0), this would ensure the Clkrs […]
I am still confused. As per tigerlake's chip.h, 0 corresponds to PCH Root port. But the code here marks it as unused. This seems conflicting information.
If PcieClkSrcUsage cannot be set to 0, then can you please update the comment in tigerlake's chip.h