[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Implement WA for DDR5 DIMM modules

[Meera Ravindranath (Code Review)]

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Angel Pons, Patrick Rudolph.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )

Change subject: soc/intel/alderlake: Implement WA for DDR5 DIMM modules
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Patch Set 22:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/50996/comment/c0f84310_91b74ba1 
PS21, Line 7: mb/adlrvp
> Needs update.

Ack

https://review.coreboot.org/c/coreboot/+/50996/comment/fa6dbfab_495aa649 
PS21, Line 7: Fix DDR5 Boot issue
> Probably say: Implement workaround for DDR5 DIMM modules?

Done