Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63777 )
Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg ......................................................................
soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
Typically, the SPIBAR_HSFSTS_W1C_BITS macro is used to clear all HSFSTS register bit-fields with the W1C attribute. So far SPIBAR_HSFSTS_W1C_BITS is 1 byte width hence, missed to clear SAF_CE (bit 8).
This patch expands the `SPIBAR_HSFSTS_W1C_BITS` macro to include SAF_CE (bit 8).
BUG=b:211954778 TEST=Able to build google/brya with this patch and clear SPI controller HSFSTS_CTL register Bits 0 to 4 and 8.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8 --- M src/soc/intel/common/block/fast_spi/fast_spi_def.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/63777/1
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 0be3dcd..2675d0e 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -75,7 +75,7 @@ #define SPIBAR_HSFSTS_AEL (1 << 2) #define SPIBAR_HSFSTS_FCERR (1 << 1) #define SPIBAR_HSFSTS_FDONE (1 << 0) -#define SPIBAR_HSFSTS_W1C_BITS 0xff +#define SPIBAR_HSFSTS_W1C_BITS (0xff | SPIBAR_HSFSTS_SAF_CE)
/* Bit definitions for FADDR (0x08) register */ #define SPIBAR_FADDR_MASK 0x7ffffff