[coreboot-gerrit] Change in coreboot[master]: nb/amd/agesa: define DDR3_SPD_SIZE as a common value

[Mike Banon (Code Review)]

Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44498 )

Change subject: nb/amd/agesa: define DDR3_SPD_SIZE as a common value
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44498/1//COMMIT_MSG@9 
PS1, Line 9: Move a size of DDR3 SPD memory (always 256 bytes) to a common define.
> I think there's more instances of `256` elsewhere?

Other instances of `256` are outside nb/amd/agesa, i.e.:
./src/vendorcode/amd/agesa/f16kb/AGESA.h:1612:  IN UINT8 Data[256];           ///< Buffer for 256 Bytes of SPD data from DIMM
./src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttoptsrc.c:150:  UINT8  TestBuffer[256];
(similar for f14/f15tn) and maybe some other things I've missed.

Do you think I should introduce DDR3_SPD_SIZE to these vendorcode places as well?