[coreboot-gerrit] Change in coreboot[master]: [WIP]mb/google/volteer: Disable CPU PCIE in FSP

[Shaunak Saha (Code Review)]

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42557 )

Change subject: [WIP]mb/google/volteer: Disable CPU PCIE in FSP
......................................................................

[WIP]mb/google/volteer: Disable CPU PCIE in FSP

Signed-off-by: Shaunak Saha 
Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42557/1

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index f7956c8..b18cb53 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -196,6 +196,8 @@

/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
    m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
+
+	m_cfg->CpuPcieRpEnableMask = 0;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)