Attention is currently required from: Xi Chen, CK HU, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44715 )
Change subject: soc/mediatek/mt8192: Implement dram all channel calibration ......................................................................
Patch Set 55: Code-Review+2
(6 comments)
File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44715/comment/22871751_38b2a186 PS41, Line 4045: (
(~(1 << div_shift)) […]
Ack
https://review.coreboot.org/c/coreboot/+/44715/comment/df85e290_f4d899dd PS41, Line 4571: 12
Yes, right. Confirmed with design, 12 is too big, can set to DRAM_DFS_SHU_MAX now.
Ack
https://review.coreboot.org/c/coreboot/+/44715/comment/f4846485_8234a7c2 PS41, Line 4603: 9
DRAM_DFS_SHU_MAX. […]
Ack
https://review.coreboot.org/c/coreboot/+/44715/comment/05fe5cc9_7fa3c176 PS41, Line 4709: DramC Write-DBI %s
Write-DBI is one feature, we'd prefer to use "Dramc Write-DBI: %s" ?
Ack
File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44715/comment/7f8f65ea_43333a5d PS41, Line 15: (s8)
no need, can remove it.
Ack
https://review.coreboot.org/c/coreboot/+/44715/comment/6c44fd79_d51edf2d PS41, Line 378: frequency %d calibration finish
Calibration of data rate %u finished […]
Ack