[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp: Allow OS to control LTR and AER

[Shuo Liu (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85561?usp=email )

Change subject: soc/intel/xeon_sp: Allow OS to control LTR and AER
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Patch Set 5: Code-Review+1

(1 comment)

File src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl:

https://review.coreboot.org/c/coreboot/+/85561/comment/9cd76985_8961961d?usp... :
PS5, Line 41: 		Return (_SB.POSC(Arg0, Arg1, Arg2, Arg3, 0x3d, 1, 1))
Possible to have some macros to represent the value?