Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46608 )
Change subject: haswell: Add Intel TXT support in romstage ......................................................................
Patch Set 5:
Support for Haswell required some adjustments to account for differences between LT-SX and LT-CX. The biggest one is SCLEAN, since it's the only way to recover from TXT-blocked memory (without manual intervention). Looks like the memory block simply prevents the MPLL (Memory PLL) from ever powering up, which is simple but effective. To run SCLEAN in romstage, I had to adapt the ACM calling code to tear down CAR, among other stuff. I also figured out the original implementation would fail when ACM sizes were not a power of two, which I CB:44880 addressed. After trying to read reference assembly code, I decided to write a new implementation from scratch, which turned out to be much simpler and easy to read, IMHO.
I saw this reference code too and I agree it is not so simple. About the suspend/resume note there is an undocumented parameter for SCHECK for resume path. According to comments and papers it should indicate to ACM that it doesn't have to perform all the task during normal boot path.