Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6481
-gerrit
commit 8aa0579e5000182bb57e20ca17f9ad3c2dee5bbc Author: Vladimir Serbinenko phcoder@gmail.com Date: Sun Aug 3 14:51:00 2014 +0200
nehalem: Make UMA size configurable in CMOS.
All modes tested on X201.
Change-Id: I23df81523196ea3f5fdb10eb04f4496c00aaeb9f Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/mainboard/lenovo/x201/cmos.layout | 15 ++++++++++++++- src/mainboard/packardbell/ms2290/cmos.layout | 9 +++++++++ src/northbridge/intel/nehalem/raminit.c | 20 +++++++++++--------- 3 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index a0670cc..cba457f 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -97,7 +97,13 @@ entries 419 1 e 1 power_management_beeps 420 1 e 1 low_battery_beep 421 1 e 9 sata_mode -#422 562 r 0 unused + +#422 2 r 0 unused + +# coreboot config options: northbridge +424 3 e 10 gfx_uma_size + +#427 557 r 0 unused
# coreboot config options: check sums 984 16 h 0 check_sum @@ -138,6 +144,13 @@ enumerations 8 1 Primary 9 0 AHCI 9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M + # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/packardbell/ms2290/cmos.layout b/src/mainboard/packardbell/ms2290/cmos.layout index 6a8aa18..7f73e5f 100644 --- a/src/mainboard/packardbell/ms2290/cmos.layout +++ b/src/mainboard/packardbell/ms2290/cmos.layout @@ -84,6 +84,9 @@ entries 409 2 e 7 power_on_after_fail 411 1 e 9 sata_mode
+# coreboot config options: northbridge +424 3 e 10 gfx_uma_size + # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved @@ -123,6 +126,12 @@ enumerations 8 1 Primary 9 0 AHCI 9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M # ----------------------------------------------------------------- checksums
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b1356c2..74ddb4b 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3796,6 +3796,8 @@ static void dmi_setup(void) void chipset_init(const int s3resume) { u8 x2ca8; + u16 ggc; + u8 gfxsize;
x2ca8 = read_mchbar8(0x2ca8); if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) { @@ -3825,13 +3827,15 @@ void chipset_init(const int s3resume) write_mchbar16(0x1170, 0xb880); read_mchbar8(0x1210); write_mchbar8(0x1210, 0x84); - pcie_read_config8(NORTHBRIDGE, D0F0_GGC); // = 0x52 - pcie_write_config8(NORTHBRIDGE, D0F0_GGC, 0x2); - pcie_read_config8(NORTHBRIDGE, D0F0_GGC); // = 0x2 - pcie_write_config8(NORTHBRIDGE, D0F0_GGC, 0x52); - pcie_read_config16(NORTHBRIDGE, D0F0_GGC); // = 0xb52
- pcie_write_config16(NORTHBRIDGE, D0F0_GGC, 0xb52); + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* 0 for 32MB */ + gfxsize = 0; + } + + ggc = 0xb00 | ((gfxsize + 5) << 4); + + pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2);
u16 deven; deven = pcie_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3 @@ -3854,9 +3858,7 @@ void chipset_init(const int s3resume) read_mchbar32(0x30); write_mchbar32(0x30, 0x40);
- pcie_read_config8(SOUTHBRIDGE, 0x8); // = 0x6 - pcie_read_config16(NORTHBRIDGE, D0F0_GGC); // = 0xb52 - pcie_write_config16(NORTHBRIDGE, D0F0_GGC, 0xb50); + pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc); gav(read32(DEFAULT_RCBA | 0x3428)); write32(DEFAULT_RCBA | 0x3428, 0x1d); }