Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36211 )
Change subject: cpu/intel/car: Add EC software sync to Intel romstage ......................................................................
cpu/intel/car: Add EC software sync to Intel romstage
Perform EC software sync in romstage, before memory training is started. Because the ChromeOS EC will not currently perform USB-PD negotiation until it jumps to running its RW code, this allows the system to get access to more power earlier in the boot flow.
This is guarded by CONFIG_VBOOT_EARLY_EC_SYNC.
BUG=b:112198832 BRANCH=none TEST=EC software sync works in update and non-update case. No significant effect on boot time (~6 ms).
Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/36211 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/car/romstage.c 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Aaron Durbin: Looks good to me, approved
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1525233..9d19635 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -21,6 +21,7 @@ #include <commonlib/helpers.h> #include <program_loading.h> #include <timestamp.h> +#include <security/vboot/vboot_common.h>
/* If we do not have a constrained _car_stack region size, use the following as a guideline for acceptable stack usage. */ @@ -51,6 +52,9 @@ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard;
+ if (CONFIG(VBOOT_EARLY_EC_SYNC)) + vboot_sync_ec(); + mainboard_romstage_entry();
/* Check the stack. */