Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11156
-gerrit
commit 521d664c4185bdad54e1469dfab2a91bc9f30526 Author: Patrick Georgi pgeorgi@google.com Date: Mon Aug 10 22:05:09 2015 +0200
fsp1.1: stub out missing header just enough so it compiles
Change-Id: Ie3d43e19803b26a26f118806f7e2a946c524926d Signed-off-by: Patrick Georgi pgeorgi@google.com --- src/drivers/intel/fsp1_1/Kconfig | 15 ++- src/soc/intel/braswell/Kconfig | 4 +- src/soc/intel/braswell/microcode/Makefile.inc | 2 +- src/soc/intel/braswell/microcode/microcode_blob.c | 2 + src/vendorcode/intel/fsp/fsp1_1/stub/FspUpdVpd.h | 153 ++++++++++++++++++++++ 5 files changed, 170 insertions(+), 6 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 33283db..a938f83 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -43,8 +43,6 @@ config HAVE_FSP_BIN Note: Without this binary, coreboot builds relying on the FSP will not boot
-if HAVE_FSP_BIN - config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" default 0 @@ -58,6 +56,8 @@ config CPU_MICROCODE_CBFS_LOC The location (base address) in CBFS that contains the microcode update binary.
+if HAVE_FSP_BIN + config ENABLE_MRC_CACHE bool default y if HAVE_ACPI_RESUME @@ -140,6 +140,15 @@ config VIRTUAL_ROM_SIZE
endif #HAVE_FSP_BIN
+if !HAVE_FSP_BIN +config FSP_INCLUDE_PATH + string "Path for FSP specific include files" + default "src/vendorcode/intel/fsp/fsp1_1/stub" + help + The path and filename of the Intel FSP binary for this platform. + +endif #!HAVE_FSP_BIN + config CACHE_ROM_SIZE_OVERRIDE hex "Cache ROM Size" default CBFS_SIZE @@ -181,7 +190,7 @@ config FSP_USES_UPD
config GOP_SUPPORT bool "Enable GOP support" - default y + default n
config USE_GENERIC_FSP_CAR_INC bool diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4f7ed6a..4d743db 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -152,7 +152,7 @@ config ENABLE_BUILTIN_COM1
config HAVE_IFD_BIN bool - default y + default n
config BUILD_WITH_FAKE_IFD bool "Build with a fake IFD" @@ -173,7 +173,7 @@ config BUILD_WITH_FAKE_IFD
config HAVE_ME_BIN bool "Add Intel Management Engine firmware" - default y + default n help The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index da25b8b..a5e8981 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1,5 +1,5 @@ # Add CPU uCode source to list of files to build. -cpu_microcode-y += microcode_blob.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
# This section overrides the default build process for the microcode to place # it at a known location in the CBFS. This only needs to be enabled if FSP is diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c index e0aeaff..20268d4 100644 --- a/src/soc/intel/braswell/microcode/microcode_blob.c +++ b/src/soc/intel/braswell/microcode/microcode_blob.c @@ -18,5 +18,7 @@ */
unsigned microcode[] = { +#if IS_ENABLED(CONFIG_HAVE_FSP_BIN) #include <microcode/microcode_blob.h> +#endif }; diff --git a/src/vendorcode/intel/fsp/fsp1_1/stub/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/stub/FspUpdVpd.h new file mode 100644 index 0000000..ce5a9a8 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/stub/FspUpdVpd.h @@ -0,0 +1,153 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* NOTE: These definitions probably don't match the FSP-side definitions, so + * the build result won't be usable even with the FSP binary added. + * They merely act as stub to make things compile. + */ + +typedef struct { + int PcdMemoryTypeEnable; + int PcdDvfsEnable; + int PcdMemorySpdPtr; + int PcdMemChannel0Config; + int PcdMemChannel1Config; + int PcdMrcInitTsegSize; + int PcdMrcInitSpdAddr1; + int PcdMrcInitSpdAddr2; + int PcdMrcInitMmioSize; + int PcdIgdDvmt50PreAlloc; + int PcdApertureSize; + int PcdGttSize; + int PcdLegacySegDecode; +} MEMORY_INIT_UPD; + +typedef struct { + int MemoryInitUpdOffset; + int SiliconInitUpdOffset; +} UPD_DATA_REGION; + +typedef struct { + int PcdUpdRegionOffset; +} VPD_DATA_REGION; + +typedef struct { + int DimmId; + int SizeInMb; +} DIMM_INFO; + +typedef struct { + int ChannelId; + int DimmCount; + DIMM_INFO DimmInfo[16]; +} CHANNEL_INFO; + +typedef struct { + int DataWidth; + int Revision; + int MemoryType; + int MemoryFrequencyInMHz; + int ErrorCorrectionType; + int ChannelCount; + CHANNEL_INFO ChannelInfo[16]; +} FSP_SMBIOS_MEMORY_INFO; + +typedef struct { + int ISPPciDevConfig; + int ISPEnable; + int PMIC_I2CBus; + int PcdRtcLock; + int PcdLogoSize; + int PcdLogoPtr; + int PcdPchSsicEnable; + int PcdPcieRootPortSpeed; + int PcdPchUsbHsicPort; + int PcdPchUsbSsicPort; + int PcdSataInterfaceSpeed; + int Usb0Lane0Ow2tapgen2deemph3p5; + int Usb0Lane1Ow2tapgen2deemph3p5; + int Usb0Lane2Ow2tapgen2deemph3p5; + int Usb0Lane3Ow2tapgen2deemph3p5; + int Usb1Lane0Ow2tapgen2deemph3p5; + int Usb1Lane1Ow2tapgen2deemph3p5; + int Usb1Lane2Ow2tapgen2deemph3p5; + int Usb1Lane3Ow2tapgen2deemph3p5; + int Usb2Lane0Ow2tapgen2deemph3p5; + int Usb2Lane1Ow2tapgen2deemph3p5; + int Usb2Lane2Ow2tapgen2deemph3p5; + int Usb2Lane3Ow2tapgen2deemph3p5; + int Usb3Lane0Ow2tapgen2deemph3p5; + int Usb3Lane1Ow2tapgen2deemph3p5; + int Usb3Lane2Ow2tapgen2deemph3p5; + int Usb3Lane3Ow2tapgen2deemph3p5; + int Usb2Port0PerPortPeTxiSet; + int Usb2Port0PerPortTxiSet; + int Usb2Port0IUsbTxEmphasisEn; + int Usb2Port0PerPortTxPeHalf; + int Usb2Port1PerPortPeTxiSet; + int Usb2Port1PerPortTxiSet; + int Usb2Port1IUsbTxEmphasisEn; + int Usb2Port1PerPortTxPeHalf; + int Usb2Port2PerPortPeTxiSet; + int Usb2Port2PerPortTxiSet; + int Usb2Port2IUsbTxEmphasisEn; + int Usb2Port2PerPortTxPeHalf; + int Usb2Port3PerPortPeTxiSet; + int Usb2Port3PerPortTxiSet; + int Usb2Port3IUsbTxEmphasisEn; + int Usb2Port3PerPortTxPeHalf; + int Usb2Port4PerPortPeTxiSet; + int Usb2Port4PerPortTxiSet; + int Usb2Port4IUsbTxEmphasisEn; + int Usb2Port4PerPortTxPeHalf; + int PcdSataClkSsc; + int PcdDispClkSsc; + int PcdUsb3ClkSsc; + int PcdEmmcMode; + int DptfDisable; + int ChvSvidConfig; + int PunitPwrConfigDisable; + int GpioPadInitTablePtr; + int GpioFamilyInitTablePtr; + int PcdGraphicsConfigPtr; + int PcdEnableI2C0; + int PcdEnableI2C1; + int PcdEnableI2C2; + int PcdEnableI2C3; + int PcdEnableI2C4; + int PcdEnableI2C5; + int PcdEnableI2C6; + int PcdEnableDma0; + int PcdEnableDma1; + int PcdEnableLpe; + int PcdEnableXhci; + int PcdEnableSata; + int AzaliaConfigPtr; + int AzaliaVerbTablePtr; + int PcdEnableAzalia; + int PcdEnableHsuart0; + int PcdEnableHsuart1; + int PcdSdcardMode; + +} SILICON_INIT_UPD; + +enum { + MEM_LPDDR3, + MEM_DDR3, +};