[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms

[John Zhao (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Shreesh Chhabbi, Ravishankar Sarawadi, Tim Wawrzynczak, Shamile Khan, Patrick Rudolph, Divya S Sasidharan,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43980

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms
......................................................................

soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms

There are known limitations for D3Cold enabling on pre-QS platform. This
change reads cpu id and disables TCSS D3Cold for pre-QS platform. For
QS platform, D3Cold enabling will be based on mainboard configuration.

BUG=None
TEST=Verified D3Cold is disabled for pre-QS (cpu:806c0) and enabled for
QS (cpu:0x806c1) if platform TcssD3ColdEnable is set to 1.

Signed-off-by: John Zhao 
Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/43980/3