[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/common/block/pmc: Fix compilation error with MS4V=BIT(18)

[Saurabh Mishra (Code Review)]

Attention is currently required from: Saurabh Mishra, Subrata Banik.

Hello Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84142?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/common/block/pmc: Fix compilation error with MS4V=BIT(18)
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soc/intel/common/block/pmc: Fix compilation error with MS4V=BIT(18)

On a 64-bit system, 1ul will typically be 64 bits wide.
The left shift can accommodate values of x up to 63 without overflowing.
But `GEN_PMCON_A` register width is 32-bit hence, adding narrow
typecasting to limit the register to max 32-bit width.

Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Signed-off-by: Saurabh Mishra 
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M src/soc/intel/common/block/pmc/pmclib.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84142/2