[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Use `postcar_enable_tseg_cache`

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45924 )

Change subject: nb/intel/sandybridge: Use `postcar_enable_tseg_cache`
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Patch Set 2: Code-Review-2

(1 comment)

On hold until the purpose of caching what is marked as TSEG is clear.

https://review.coreboot.org/c/coreboot/+/45924/2/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/memmap.c:

https://review.coreboot.org/c/coreboot/+/45924/2/src/northbridge/intel/sandy... 
PS2, Line 54: Cache the TSEG region using regular MTRRs. This is only useful
            : 	 * when SMRRs are not supported,
> I don't think this is true. […]

Hrm, good point.