[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Fix typo mistake in cache_as_ram.S

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34818 )

Change subject: soc/intel/common: Fix typo mistake in cache_as_ram.S
......................................................................

soc/intel/common: Fix typo mistake in cache_as_ram.S

Change-Id: I14c0e87012bdbaaff50844ed097b66e2221b1e08
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/34818/1

diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index b1648e8..d5f5081 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -365,7 +365,7 @@
    jnz	find_llc_subleaf

/*
-	 * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE
+	 * Set MSR 0xC91 IA32_L3_MASK_1 = 0xE/0xFE/0xFFE/0xFFFE
     * for 4/8/16 way of LLC
    */
    shr	$22, %ebx