Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32219
Change subject: mb/google/hatch: Support 16MiB fmap ......................................................................
mb/google/hatch: Support 16MiB fmap
Add an config and a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flashroms.
BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap'
Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen philipchen@google.com --- M src/mainboard/google/hatch/Kconfig A src/mainboard/google/hatch/chromeos-16MiB.fmd 2 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32219/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 041ac2d..dd400b9 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -24,6 +24,11 @@
if BOARD_GOOGLE_BASEBOARD_HATCH
+config HATCH_HAS_16MB_FLASH + bool "Build for a board with a 16MiB SPI flash" + default n if BOARD_GOOGLE_HATCH_WHL || BOARD_GOOGLE_HATCH + default y + config CHROMEOS bool default y @@ -54,6 +59,11 @@ config UART_FOR_CONSOLE default 0
+config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if HATCH_HAS_16MB_FLASH + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + config GBB_HWID string depends on CHROMEOS diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd new file mode 100644 index 0000000..1594ab3 --- /dev/null +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd @@ -0,0 +1,42 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + SI_BIOS@0x400000 0xc00000 { + RW_SECTION_A@0x0 0x380000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x36ffc0 + RW_FWID_A@0x37ffc0 0x40 + } + RW_SECTION_B@0x380000 0x380000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x36ffc0 + RW_FWID_B@0x37ffc0 0x40 + } + RW_MISC@0x700000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0x730000 0xd0000 + WP_RO@0x800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x30c000 + } + } + } +}