[coreboot-gerrit] [XS] Change in coreboot[main]: mb/goog/brox: unlock gpio wake sources

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83951?usp=email )

Change subject: mb/goog/brox: unlock gpio wake sources
......................................................................

mb/goog/brox: unlock gpio wake sources

The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source.  This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.

BUG=b:360380950, b:359692570
BRANCH=None
TEST=verify brox DUT is able to power down and stay powered down when
selecting the "Power off" button in the firmware dev screen.

Change-Id: I5cd36640677996209beb8fe29f522ff8e07ebf00
Signed-off-by: Nick Vaccaro 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83951
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
---
M src/mainboard/google/brox/variants/jubilant/gpio.c
M src/mainboard/google/brox/variants/lotso/gpio.c
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Eric Lai: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/brox/variants/jubilant/gpio.c b/src/mainboard/google/brox/variants/jubilant/gpio.c
index 0540cd1..a8e652c 100644
--- a/src/mainboard/google/brox/variants/jubilant/gpio.c
+++ b/src/mainboard/google/brox/variants/jubilant/gpio.c
@@ -41,7 +41,7 @@
    /* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> FPMCU_RST_J_SUB_L (active low) */
    PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
    /* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 NF6: USB_C_GPP_F15] ==> FP GSPI INT  */
-	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT),
    /* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==>  FP GSPI CLK */
    PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG),
    /* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL
diff --git a/src/mainboard/google/brox/variants/lotso/gpio.c b/src/mainboard/google/brox/variants/lotso/gpio.c
index c85363d..0b98286 100644
--- a/src/mainboard/google/brox/variants/lotso/gpio.c
+++ b/src/mainboard/google/brox/variants/lotso/gpio.c
@@ -34,7 +34,7 @@
    PAD_NC(GPP_E15, NONE),
    /* GPP_E18 : [NF1: DDP1_CTRLCLK NF4: TBT_LSX0_TXD NF5: BSSB_LS0_RX
     * NF6: USB_C_GPP_E18] ==> SOC_FPMCU_INT_L */
-	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_E18, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E18, NONE, PWROK, LEVEL, INVERT),
    /* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX
     * NF6: USB_C_GPP_E20] ==> EN_FP_PWR */
    PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),