Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70238 )
Change subject: mb/google/brya: Set power limit values for kano and zydron ......................................................................
mb/google/brya: Set power limit values for kano and zydron
Add the RPL CPU power limits to kano and zydron's power limit table.
BUG=b:261127266 BRANCH=brya TEST="emerge-brya coreboot chromeos-bootimage", flash zydron with image-zydron.serial.bin and verify zydron boots successfully to kernel.
Change-Id: I369c5d7a9a3db0c3e7184a23b0f159ed715b5a50 Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/70238 Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com Reviewed-by: Tyler Wang tyler.wang@quanta.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/brya/variants/kano/ramstage.c M src/mainboard/google/brya/variants/zydron/ramstage.c 2 files changed, 25 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tyler Wang: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/kano/ramstage.c b/src/mainboard/google/brya/variants/kano/ramstage.c index aa48a9d..c0f126f 100644 --- a/src/mainboard/google/brya/variants/kano/ramstage.c +++ b/src/mainboard/google/brya/variants/kano/ramstage.c @@ -9,6 +9,8 @@ { PCI_DID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 18000, 20000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 18000, 20000, 43000, 43000, 105000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 12000, 15000, 40000, 40000, 114000 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 12000, 15000, 40000, 40000, 114000 }, };
void variant_devtree_update(void) diff --git a/src/mainboard/google/brya/variants/zydron/ramstage.c b/src/mainboard/google/brya/variants/zydron/ramstage.c index aa48a9d..c0f126f 100644 --- a/src/mainboard/google/brya/variants/zydron/ramstage.c +++ b/src/mainboard/google/brya/variants/zydron/ramstage.c @@ -9,6 +9,8 @@ { PCI_DID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_5, 28, 18000, 20000, 43000, 43000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_3, 28, 18000, 20000, 43000, 43000, 105000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 12000, 15000, 40000, 40000, 114000 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 12000, 15000, 40000, 40000, 114000 }, };
void variant_devtree_update(void)