Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31950 )
Change subject: device/pciexp_device: Add set_subsystem() for pciexp device ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31950/2/src/include/device/pciexp.h File src/include/device/pciexp.h:
https://review.coreboot.org/#/c/31950/2/src/include/device/pciexp.h@6 PS2, Line 6: #define PCIE_SUBSYSTEM_VENDOR_ID 0x94
Please reference the PCIe specs for register 0x94. […]
can you please access link https://www.intel.com/content/www/in/en/design/products-and-solutions/proces...
to download product specification
i can see those 2 registers in PCI and PCIE config space details as below
0x2c: in general PCI controller like PMC, SMBUS etc.
Bit Range Default & Access Field Name (ID): Description 31:16 0h RW/O Subsystem ID (SSID): Written by BIOS. Not used by hardware. This field is reset by PLTRST# assertion. 15:0 0h RW/O Subsystem Vendor ID (SSVID): Written by BIOS. Not used by hardware. This field is reset by PLTRST# assertion
0x94: for PCIE controller
Bit Range Default & Access Field Name (ID): Description 31:16 0h RW/O Subsystem Identifier (SID): Indicates the subsystem as identified by the vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). 15:0 0h RW/O Subsystem Vendor Identifier (SVID): Indicates the manufacturer of the subsystem. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset).