Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17803
-gerrit
commit 803f841b7924658b334bebe64083beec0958ec6f Author: Aaron Durbin adurbin@chromium.org Date: Mon Dec 12 14:12:22 2016 -0600
mainboard/google/reef: implement phase enforcement pin
On upcoming boards an optional pull up is applied on GPIO_10 to indicate if the board should have security features locked down for a shipping system. Provide a weak pull down so that all boards will indicate a logic 0 until the stronger pull up resistor is stuffed.
BUG=chrome-os-partner:59951 BRANCH=reef
Change-Id: I6f514a69bccd05ca02480f3c30d0ad503a955b1e Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/mainboard/google/reef/variants/baseboard/gpio.c | 3 ++- src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index ae84e9c..d5e5917 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -282,7 +282,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_8, UP_20K, DEEP),
PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */ - PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* Board phase enforcement */ PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */ @@ -381,6 +381,7 @@ variant_sleep_gpio_table(size_t *num) static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), + CROS_GPIO_PE_AH(PAD_N(GPIO_SHIP_MODE), GPIO_COMM_N_NAME), };
const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h index ca6aa31..1db7422 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h @@ -38,6 +38,8 @@ /* Write Protect and indication if EC is in RW code. */ #define GPIO_PCH_WP GPIO_75 #define GPIO_EC_IN_RW GPIO_41 +/* Determine if board is in final shipping mode. */ +#define GPIO_SHIP_MODE GPIO_10
/* Memory SKU GPIOs. */ #define MEM_CONFIG3 GPIO_45