Hello Raul Rangel, Chris Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/42216
to review the following change.
Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ......................................................................
soc/amd/picasso: Add UPD xhci0_force_gen1
Add xhci0_force_gen1 UPD for force USB3 port to gen1
BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build.
Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+... Reviewed-by: Raul E Rangel rrangel@chromium.org Reviewed-by: Furquan Shaikh furquan@chromium.org --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42216/1
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e52751a..f5fbe0f 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -103,6 +103,8 @@ SD_EMMC_EMMC_HS400, SD_EMMC_EMMC_HS300, } sd_emmc_config; + + uint8_t xhci0_force_gen1; };
typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 2d83220..e0620e5 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -95,6 +95,12 @@ fill_ddi_descriptors(scfg, fsp_ddi, num_ddi); }
+static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, + const struct soc_amd_picasso_config *cfg) +{ + scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; +} + void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { const struct soc_amd_picasso_config *cfg; @@ -103,4 +109,5 @@ cfg = config_of_soc(); fsps_update_emmc_config(scfg, cfg); fsp_fill_pcie_ddi_descriptors(scfg); + fsp_usb_oem_customization(scfg, cfg); }