Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58068 )
Change subject: soc/amd/cezanne/include/southbridge: add some more PM register defines ......................................................................
soc/amd/cezanne/include/southbridge: add some more PM register defines
Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Ib109efe679560604ff8209b4177611eb2aa9ebdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/58068 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/cezanne/include/soc/southbridge.h 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 31387b6..8a1150e 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -47,11 +47,15 @@ #define PM_ACPI_BIOS_RLS BIT(7) #define PM_ACPI_PWRBTNEN_EN BIT(8) #define PM_ACPI_REDUCED_HW_EN BIT(9) +#define PM_ACPI_S5_LPC_PIN_MODE_SEL BIT(10) +#define PM_ACPI_S5_LPC_PIN_MODE BIT(11) #define PM_ACPI_BLOCK_PCIE_PME BIT(24) #define PM_ACPI_PCIE_WAK_MASK BIT(25) #define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_SPI_PAD_PU_PD 0x90 +#define PM_ESPI_CS_USE_DATA2 BIT(16) #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1)